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Physical Methods of Speed-Independent Module Design
Oleg Izosimov
INTEC Ltd, Room 321, 7a Myagi Street, Samara 443093, Russia1. Introduction
Any method of logic circuit design is based on using formal models of gates and wires. The simplest model of a gate is determined by only two "parameters": (a) Boolean function is to be calculated, (b) fixed propagation delay. The simplest model of a wire is an ideal medium with zero resistance and consequently, with zero delay. Such simple models allow circuit design procedures which are a sequence of elementary steps easily realized by a computer.
When logic circuits designed by using the simplest models expose unreliable operation as in the case of gate delay variations, designers introduce less convenient but more realistic models with arbitrary but finite delay. Using more complicated models may produce logic circuits that are called speed-independent [1].
In speed-independent circuits transition duration can be arbitrary. So a centralized clock cannot be used. Instead special circuitry to detect output validity is applied. Besides, additional interface circuitry is needed to communicate with the environment in a handshaking manner. A speed-independent circuit can be seen as a module consisting of combinational logic (CL) proper, CL output validity detector (OVD) and interface circuitry (Fig.1). To enable OVD to distinguish valid output data from invalid ones, the redundant coding scheme was proposed [2]. The main idea of the scheme is to enumerate all possible input and output data, both valid and invalid. The OVD must be provided with appropriate information on data validity. To realize the idea of redundant coding some constraints on CL design are imposed [3]:
(i) CL must be free of delay

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